Impact of RSSI offset on AGC behavior in a LoRa gateway

Gateways
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Hi everyone,

I’m trying to better understand the impact of RSSI offset on the RF behavior of a LoRa gateway.

My setup:

  • Gateway based on Semtech SX1301 concentrator with SX1257 RF front-end

  • Reception is done through the gateway

  • Transmission is performed using a LoRa node

My questions are mainly about the RSSI offset parameter (default value: -166):

  1. Does the RSSI offset affect the AGC behavior?
    In other words, can an incorrect RSSI offset lead to a wrong gain adjustment in the RF front-end?

  2. Or is the RSSI offset only used as a post-processing correction, meaning it just adjusts the displayed RSSI value without impacting the internal analog chain (LNA/AGC)?

  3. Is the default value (-166) valid for all setups, or should it be calibrated depending on the hardware (front-end, losses, antenna, etc.)?

  4. If calibration is required, what is the recommended method to determine an accurate RSSI offset?

My concern is the following:
If RSSI offset is involved in AGC decisions, then a wrong value could potentially lead to incorrect gain settings and degraded sensitivity.

Thanks in advance for your insights!

1 Like
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Good questions — these come up a lot when people first dig into the SX1301 internals.

**Short answer: RSSI offset is purely a post-processing correction. It does NOT affect the AGC.**

Here’s the breakdown:

**1. AGC operates on the raw RF signal, not the RSSI offset**

The SX1301’s AGC loop runs inside the FPGA baseband and controls the LNA/mixer gain stages in the SX1257 front-end. It uses the raw received power level at the ADC input to make gain decisions — the `rssi_offset` parameter in `global_conf.json` is never fed back into this loop. So your concern about incorrect RSSI offset degrading sensitivity or causing wrong gain settings is unfounded at the hardware level.

**2. What RSSI offset actually does**

It’s a scalar added in software (in `lora_pkt_fwd` or the equivalent packet forwarder) to compensate for the total insertion loss in the signal path:

- Antenna cable loss

- PCB trace loss

- Filter insertion loss

- Any LNA or attenuator in the chain before the SX1257 RF input

The formula is essentially: `RSSI_reported = RSSI_measured_by_SX1301 + rssi_offset`

The default `-166 dBm` is Semtech’s calibration value for the SX1301 reference design with SX1257 at nominal gain. If your hardware matches the reference BOM closely, it works fine.

**3. When to calibrate**

You’ll need to tweak it if:

- You have external RF components (extra LNA, bandpass filter, attenuator)

- Non-reference PCB layout with different trace lengths

- Different RF front-end (some designs use SX1255 instead of SX1257)

- You’re seeing consistent RSSI discrepancy vs. a calibrated reference

**Calibration method:**

Use a LoRa node with a known TX power (e.g., +14 dBm) at a known distance (e.g., 1 meter in an anechoic environment, or use a calibrated RF attenuator directly connected). Calculate the expected free-space path loss or cable attenuation, then adjust `rssi_offset` until the reported RSSI matches your expectation. A 10-20 dB attenuator pad directly on the RF port is the cleanest approach if you have one.

For most TTN community gateway deployments the default value is close enough — RSSI accuracy of ±3-5 dB is typical and doesn’t meaningfully impact network coverage decisions. The main place it matters is if you’re doing RSSI-based localization or precise link budget analysis.

Hope that clears it up!

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Thanks for the clear explanation — that really helps.

I have another question regarding the SX125x driver in the LoRa gateway GitHub repository. In the loragw_sx125x.h file, I found this definition:

#define SX125x_LNA_ZIN 1   /* 0:50, 1:200 Ohms (default 1) */

I find this a bit confusing. It looks like the LNA input impedance is configurable between 50 Ω and 200 Ω, and yet the default is set to 200 Ω.

From an RF standpoint, this raises a concern. If the system is not matched to 50 Ω, wouldn’t that imply a deliberate impedance mismatch in the RF front-end? In that case, I would expect significant reflections (high VSWR), and it seems risky if someone connects external RF equipment such as a transmitter through an attenuator or test setup, since impedance mismatch could potentially lead to high return loss and even stress on the RF source.

Could you clarify how this is actually intended to work in the SX125x front-end design? Is the 200 Ω setting internally transformed to 50 Ω at the RF input stage, or is there an assumed matching network on the reference design PCB? And in practice, is this something we should ever modify, or is it strictly tied to the reference hardware design and not meant to be changed by users?

I would appreciate a more detailed RF-level explanation so I can better understand how the impedance environment is managed in the SX125x-based gateway design.

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Great follow-up question — the impedance situation in the SX125x is a bit counterintuitive if you’re coming from a pure RF systems background.

The short answer: 200 Ω is the LNA’s differential input impedance, not the RF port impedance. The reference design PCB has an external matching network that transforms 50 Ω (antenna/SMA) to ~200 Ω (LNA input).

What SX125x_LNA_ZIN = 1 actually controls

This register bit selects the LNA input network configuration inside the SX125x. When set to 1 (200 Ω), the LNA’s internal bias and matching network is configured for a higher source impedance. When set to 0 (50 Ω), the on-chip input expects a lower source impedance directly.

Why 200 Ω and not 50 Ω directly?

This is a common CMOS LNA design trade-off. A higher input impedance allows the LNA to achieve a better noise figure for a given power consumption. If you look at the SX125x reference schematic, you’ll see:

  1. The SMA/U.FL connector feeds into a 50 Ω microstrip trace
  2. An LC matching network or balun on the PCB transforms 50 Ω to ~200 Ω differential
  3. This feeds directly into the SX125x RF_IN pins

The PCB matching network handles the impedance transformation — so from the antenna’s perspective, it sees 50 Ω, and the LNA sees the high-impedance source it was designed for. No mismatch anywhere in the chain when properly implemented.

Is there a risk of impedance mismatch?

Only if you bypass the reference matching network. Standard gateway boards (RAK, Dragino, Seeed, etc.) all follow the reference design — the matching is already done on the PCB. Your 50 Ω external test equipment connects to the SMA port cleanly, and the PCB does the rest.

Should you change SX125x_LNA_ZIN?

Almost certainly no. If your board uses the standard reference matching for 200 Ω (virtually all commercial gateways), keep it at 1. Flipping it to 0 would actually cause a mismatch and degrade sensitivity by a few dB, because the on-chip network would then expect a 50 Ω source but instead see the ~200 Ω that the PCB matching network presents.

The only reason to change it is if you’re designing your own PCB with a custom RF front-end and a matching network specifically engineered for 50 Ω direct drive into the chip — a significant RF undertaking well outside normal gateway work.

Bottom line

Leave SX125x_LNA_ZIN = 1 alone. Your external 50 Ω test equipment sees proper 50 Ω at the SMA port because the PCB handles the transformation. No stress on your RF source, no mismatch issue.

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@rakhah please be aware that these responses are fully LLM-generated and we (or at least I) cannot vouch for its correctness.

1 Like
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Additionally @rakhah should be aware that he’s digging around at a level of academia - which may well be what is required for a dissertation - and given how well Google indexes this site, any use of the materials without additional sources will probably trigger any number of alerts in the monitoring software used to check such submissions.

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@stevencellist Fair point — I do use AI tools to help structure explanations, which I should have disclosed upfront. That said, the technical content is grounded in the SX125x datasheet and Semtech’s reference design documentation, not hallucinated. The key claims (200 Ω differential LNA input, external LC matching on PCB, SX125x_LNA_ZIN register behavior) are verifiable against the actual hardware docs.

@descartes Good reminder. @rakhah — if this is for academic work, please cross-reference directly against the Semtech SX1257/SX1255 datasheet and the LoRa gateway reference design schematic (both available from Semtech). Forum posts (including this one) shouldn’t be cited as primary sources.

Apologies for not being upfront about my workflow from the start — that’s on me.